Successive approximation register (SAR) analog-to-digital converters (ADC) require digital-to-analog converters (DAC) which produce precise reference values to determine the digital equivalent of an analog input signal. One of the primary factors limiting the ultimate speed of SAR-based ADCs is the settling time of the DAC. For proper operation, the DAC must settle to a voltage level that is accurate to at least as many bits as the resolution of ADC. In resistor string DACs, the precise reference voltage is produced by tapping across the appropriate nodes in a series-connected string of resistors. The settling time is determined by the net resistance, the capacitance that must be driven at that node, and the change in applied voltage. These conflicting criteria must be chosen for each design to optimize DAC performance.
State-of-the-art resistor string DACs use a single switch size for each node selection switch in the resistor chain. This size is selected to optimize overall device speed and is dependent upon the size of the unit resistor in the DAC. This chosen FET size produces a small parasitic capacitance at each node, with the sum of the output node capacitance from all of the switches traded against the maximum total resistance to ground from the output node. For the typical switch size, the on-resistance of the FET can be comparable to the resistance of the resistor chain. Thus the device settling time can be optimized for some nodes, but can be greatly limited by the FET on-resistance at other nodes. The worst-case settling time will be at the MSB case. This case requires the largest possible change in voltage at the output node (nominally one-half that of the reference supply voltage). In addition, the resistance of the selected node to ground will be one-half that of the total resistor chain, which is the largest possible value. Thus the maximum RC time constant will be associated with the MSB.